When simulating your design, putting everything into the simulation is often a finishing step.
You're not at that point of the design yet, and it's a real pain in the butt.
I prefer idealistic building blocks. they make things much quicker.
so let me diminstrate how I would break this problem down.
after a long time in the field, most of this has become second nature and doesn't require much planning.
its gona take a lot longer to write than to execute.
ultimately, we want a simple buck converter.
this implies we need a pulse width modulated switched power source.
(There are many pwm topologys. Im going to stick with a fixed frequency and varable duty cycle to keep this quick).
we want to drive an n-channel mosfet.
this is the first set of constraints given to us. pull the datasheet
( IRF9540), and we have a
max VDS -100V
VGS(th) -2V ~ -4V
max Vgs +/- 20V
RDS(on)Vgs=-10V 200 mOhm
Td(on) 16ns
Tr 73ns
Td(off) 34ns
Tf 57ns
Rg 1.6 ohms
Qgd 29nC
good stuff, good stuff.
I just now realized you're using a p-channel device.
all the same maths, tho
so we need to drive the gate to less than Vcc - 10V to get that low impedance path to Vcc of 0.20 ohms
easy math here, so expect me to get it wrong.
simulation will correct me.
we have a Vcc of 19 - 10 = 9V
$$ \frac{0.000000029}{9}= 3.2nF $$
so the parasitic gate capacator will be about 3.2nF.
(I really think i just use the delta, which would be 10V and 2.9nf,
but let's go with 9V 3.2nF). Little explanation, the charge required to turn the mosfet fully on is given in columbs, i just converted it to frads.
F=q/v
not only do we need Vcc-10V but we have to do it through a parasitic
resistance of 1.6 ohms (not all datasheets give this number, must be an rf
component)
this equals an ideal charge time of 25ns(20MHz) and a rms of 47.3mA peeking at
6250mA
if we want a 60kHz switching frequency, let's target a switching speed 100x that.
For a 16.6us switching frequency, let's target a 166ns switching speed.
if 5*r*c=t
then t/(5c)=r
so 0.000000166÷(5×0.0000000032) = 10.375 ohms
and to doublecheck 5×10.375×0.0000000032=166ns
(so the 5rc is the time it takes to 98% charge a capacator.
just so everyone is on the same page)
this will have an instant current draw of 1034mA and an rms of 6.5mA
so what do these numbers mean?
if we drive the mosfet 'on' in 166ns, it takes (16+73= 89ns) for the gate charge to
take effect and the output to fully rise, so the total transition time between fully off
to fully on will be around 255ns.
to go from fully on to off would be 166+34+57=257ns.
in worst case, we will spend 512ns out of 16.6us in a switching state.
that is about 3% of the duty cycle, just switching
which is about 3% of our alloted time, in the most energy inefficient state, worst
case scenario, we are zero % efficient for 3% of the time, and we have an ideal
efficiency of 97%.
really it will be less b/c those values in the datasheet is for a fast transition, and we will be doing a particularly slow transition. Which is good,
we can say that theoretical +97%
base line, we know we need to feed the mosfet driver with 1034mA(6.5mA rms)of current to get this done.
your drawing says your using BC327 and BC337 after reading the datasheet, your
going to need to parrallel them to get the current needed. which is a terrible idea. (https://youtu.be/0ZG11UBoj-o)
max current is 800ma and you need to push 1034.
2 in parallel tempature coupled should do the trick.
so they have a high hfe of >100. meaning if you apply 10ma at the base
you get 1000ma at the emitter. i would seriously consider setting up independent
base resistors and bonding the collectors to smoke at least 1 set before switching
to a properly rated part. if parts arnt flyin, are you tryin?
We will/may need to add some emmitor resistors of low value, (2-5ohms) to prevent
overdriving the drivers but ignore that for now .
simulation time.
https://everycircuit.com/circuit/4609478892847104
notice the 115ma crossover distortion,
this will blow the transistors, their already maxed out.
so we need to introduce a delay to allow the on transistors to fully switch off before
turning the off transistors fully on.
if we parrallel the transistors base with a small capacator, this will delay its on time,
then if we shunt the base resistors with a diode, this will decrease its off time.
https://everycircuit.com/circuit/5579716065099776
there is still a little minor crossover distortion but now the shunted current is less than 1ma for less than 1ns so only your electrician will know.
(looks great from the house)
so timeing and current are checked. now lets focus on voltage. spec says Vcc-10 and we are currently dropping 20.
there are a few ways to tackle this problem, datasheet says +/- 20, and we could
ignore it, but we will be within 85% of absolute maximum, so no.
we could use a rubber diode but this can effect our current draw. so no.
we can prep a new voltage plane and use it as ground for the sinking portion of the
driver cycle. shore it up for the high inrush current all without effecting performance. (to the bus)
https://everycircuit.com/circuit/4839481706414080
See what I did there, it will be a pain in the but to implement but for now, we model it as another voltage source, do the hard stiff later
notice how we had to lift the current sink driver circuit by 10V to maintain proper
Vbe biasing, and how I had to half the base resistors, because of the voltage difference.
basicly instead of dealing with a 20v system, we are dealing with a 10v system that starts at 10v up.
simulation allows us to quickly implement the 'ideal' solution for a problem without
having to involve every little perfect detail.
as we approach the next problem, just rinse and repeat the process. use the maths, you do not need a super computer.
so sleepy. got class then work ill add more when I get time, we still got to fully implment the mosfet into the ciruit. |
