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arsphenamine
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[*] posted on 17-10-2010 at 13:34
Yet Another Halbach Array Simulation


This is a field plot from the .25" center of aliced25's Halbach array, whose FEM file is attached at the end.
There were changes:
  • Magnets are N40.
  • Magnets are 2" in the major dimension.
  • Magnets are separated by at least .001" so FEMM42
    doesn't crash from OOM and/or truncation errors.

As you can see, the field is 10501.6 gauss +/- 0.3 gauss,
a range similar to the earth magfield strength magnitude.
In a 1T field, a +/- 0.3 gauss range is equivalent to a 2.5kHz shift.

This image was generated by gnuplot since Femm42's graph
generator won't resolve y-axis legends finer than 1 Gauss.



Femm42 base file Attachment: halbach02.fem (4kB)
This file has been downloaded 798 times
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[*] posted on 17-10-2010 at 22:05


That's pretty good for a simulation. Now you just need something to cancel the hump, maybe put a current through it (once you've got 1T or so to begin with, a few mT here and there is only a few mA away) so it can be varied / tuned.

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[*] posted on 17-10-2010 at 23:08




In terms of frequency synthesis, the programmable CDCE-706 3-PLL Multiplier/Divider used in the Diophantine paper looked good, then I found the use of all 3 PLL's in a Cascaded Diophantine setup, where the mixer generates a complete frequency with the addition of the 3rd PLL input. Now that is effectively modulation is it not? We could run the DAC in through the 3rd PLL and that could take it right up to the necessary excitation/pll frequency? Does the DAC have to be outputting the 43MHz all by itself or can it be set on a carrier band of, say, 43MHz? That would mean that fairly low speed (ie. Audio) DAC's could be used, if the carrier wave was left on during the collection of the resonance signal, wouldn't that help to cancel out a lot of the echo/noise? This is what it says on the 3-PLL sheet:


Quote:

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs.


Now I cannot understand why there are products from 3 different manufacturers on the board with the Diophantine synthesizer, I'd be of a mind to utilize as few suppliers as possible. That said, the MAX-2306 IQ Demodulator would enable us to remove the carrier wave and access the signal.

There is also a 2-PLL version of the CDCE-706, being the CDCE-925, which we could presumably use for the direct frequency of the carrier wave (per the Diophantine model) and add the signal to be carried at the mixer (10kHz sine wave @ several watts - ain't hard with audio speakers, you can even get Digital Input Class D Analog Output). (Dumbarse - I put 100kHz & that ain't audio).

PS The use of a PLL to clean up after DDS ain't exactly novel (It is in products like here, while Analog Devices discusses the use of upconversion of a DDS Signal by multiplication thereof to the UHF band.

In terms of this project, that would work too - low speed audio DACs at full-throttle, upconverted to 0.43 or 4.3GHz, then downconverted through the dual PLL (/10 or /100), multiplication adds noise, division reduces it, so a SAW filter (several MHz bandwidth - Oscilent has claims on +/- 2MHz bandwidth on the 430MHz range) between the two would be good. Ideally if the bandwidth was narrowed to several MHz prior to downconversion (and everything is in phase due to the PLL), it should be possible to narrow the bandwidth of the downconverted signal significantly (+/- 200kHz?, so what 0.4MHz wide?).

@ 12AX7 & arsphenamine

You can cancel the hump out by turning the 4 circular magnets, however it will only go so far. That said the circular magnets take up the manufacturing tolerances (in practice) as well (I've been quoted on a shitload of magnets and most want 5% tolerances). Be aware that as you turn each magnet it alters the field around the others (as do any shims).

PS If anyone has knowledge of a working torrent for FEMLAB/COMSOL I'd be willing to view it (not that I'd misuse it, promise:P). I'd be interested to model the whole thing in 3D

[Edited on 18-10-2010 by aliced25]

[Edited on 18-10-2010 by aliced25]
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[*] posted on 18-10-2010 at 08:13


Quote: Originally posted by 12AX7  
That's pretty good for a simulation. Now you just need something to cancel the hump, maybe put a current through it (once you've got 1T or so to begin with, a few mT here and there is only a few mA away) so it can be varied / tuned.Tim
Thanks.

Note that the simulation includes some realistic air space since
any one smooth machined surface is usually good within 1 mil flatness
irrespective of its major dimensional (in)accuracies.

Estimations for a simplified shim coil for +/ 2.5 Gauss correction
revealed that they generate a little heat that must be accounted for.

For a 1" diameter coil of 100 turns of #42 in 10 layers at 10 turns per layer,
generating 2.5 Gauss incurs a self-heating of 5 ° C per 2.75 hours.
(specs: 43 ohms, at 2ma, 87mv, a copper volume of 0.5cc)

The magnet array conducts most of this and reaches an undetermined
steady state temperature from air convection cooling. Its field degrades
0.11%/°C, some 11 Gauss/°C for the 1T Halbach, or -47 kHz/°C.

The shim coils may be better off in aluminum formers instead of on Kapton.

A prudent course may be to treat the inhomogeneity sepArately from bulk
field drift due to temperature changes.

Of course, these crappy little heating effects went away when NMR
technology shifted to superconductors.
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[*] posted on 18-10-2010 at 10:14


Quote: Originally posted by aliced25  
You can cancel the hump out by turning the 4 circular magnets, however it will only go so far. That said the circular magnets take up the manufacturing tolerances (in practice) as well (I've been quoted on a shitload of magnets and most want 5% tolerances). Be aware that as you turn each magnet it alters the field around the others (as do any shims).
1.Your Halbach design is amenable to a few 1/4'dia by 1/32" thick button magnets.
FEMM results suggest +/- 0.1 Gauss at the sweet spot.

2. Where the fsck are you spec'ing magnets?!
I hope that 5% refers to remanence/coercivity and not physical dimensions.

Note that the last two sig figs on the B axis are fractional Gauss.



Perhaps adding a 1/8" wide 5 mil steel strip at the magnet center might
flatten it usefully.

Stelter arrays are capable of stronger fields but with order of magnitude
worse homogeneity.

Tweaked FEM file: Attachment: halbach03.fem (5kB)
This file has been downloaded 835 times

[Edited on 18-10-2010 by arsphenamine]
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[*] posted on 18-10-2010 at 12:33


I find myself amused by your concept of simplifying - replacing a DDS chip with one or more PLLs, plus a divider, buffer, and low pass filter per PLL, and a mixer. Even with the dividers in the package, it's still more parts. Your trying to use a DAC leads to even more parts, as you need either a really high speed clock and a lot of memory, and/or a finely tunable clock, to get the control you want.

On top of that most DDS chips have 20 to 50 bit long counters, while those TI chips have 12 and 9 bit dividers. This means more messing about when you want fairly wide range and high resolution when you use the DFS method

BTW - I find it interesting that this is being treated as new, when I was taught about PLLs some 45 years ago this combination approach was one way given to generate a range of frequencies.



For a homebrew rig it's likely you'll want much wider tuning range and something of a 'zoom out' function for use during development, than is needed for actual NMR spectroscopy. I suspect that actual field strength and homogeneity will be unknown until measured, thermal and mechanical drift will have to be learned on the fly. Once you've determined those, then you can go to really narrow band filters. I'd refer you to an image I posted re theory & practice, but I've no idea what thread it was in.

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[*] posted on 18-10-2010 at 14:07


Quote: Originally posted by aliced25  


Now I cannot understand why there are products from 3 different manufacturers on the board with the Diophantine synthesizer, I'd be of a mind to utilize as few suppliers as possible.



I cannot understand why you seem to be fixated on using parts from one manufacturer only! There is no benefit in doing this. In my 20 odd years of engineering I've always used whatever was right for the job, regardless of who the supplier was. If there were multiple sources for the same part (equivalents) then so much the better.
Single source parts can easily become a manufacturer's nightmare.




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[*] posted on 18-10-2010 at 16:51


Quote: Originally posted by Twospoons  

I cannot understand why you seem to be fixated on using parts from one manufacturer only! There is no benefit in doing this. In my 20 odd years of engineering I've always used whatever was right for the job, regardless of who the supplier was. If there were multiple sources for the same part (equivalents) then so much the better.
Single source parts can easily become a manufacturer's nightmare.


And so many of them from Maxim, no less. Half the engineers I know have had to design out Maxim parts that are no longer in production, or which have dropped out of stock. Maxim is great on samples, yes... place an order for a thousand, and you'll be waiting a very long time.

Fortunately, the most common chips, like MAX232, are multiple sourced and available by the shovelful.

Tim




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[*] posted on 18-10-2010 at 17:08


Quote: Originally posted by 12AX7  
Quote: Originally posted by Twospoons  

I cannot understand why you seem to be fixated on using parts from one manufacturer only! There is no benefit in doing this.


And so many of them from Maxim, no less. Half the engineers I know have had to design out Maxim parts that are no longer in production


Y'know, you probably won't listen to this either, but sepArating the circuitry into functional modules would allow for facile revisions as obligated by hardware (un)availability.

Oscillator, transmitter, demux, converter, CPU -- each gets their own PCB.

Like, duh, how much exposition does the value of modular design require?
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[*] posted on 18-10-2010 at 18:37


Quote: Originally posted by aliced25  


PS If anyone has knowledge of a working torrent for FEMLAB/COMSOL I'd be willing to view it (not that I'd misuse it, promise:P). I'd be interested to model the whole thing in 3D

[Edited on 18-10-2010 by aliced25]


3d modelling will not just be interesting, it will be essential! End effects will be very significant, given the sensitivity of the system to any inhomogenity in the field. Unless you simply make the magnet array 1 metre deep!




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[*] posted on 18-10-2010 at 19:51


@ twospoons,

I'm trying my best to get hold of a 3D modeling solution, when I get it I'll use it. As to the wanting to minimize the number of components from various manufacturers, it is a personal preference, where there are multiple products with similar specifications, I'll always choose one that I know will work with the board (ie. from the same manufacturer). It ain't that hard to work out why, surely?

@ not_important

With the DDS chips being unfiltered and having multiple harmonic images, there is little reason to choose them over a multiple PLL design using a close-tolerance crystal running a DAC, multiply the original sine-wave to about 10-20 times the necessary wavelength (PLL 1), run it through a close-ish tolerance SAW filter (+/- 2MHz) and back through the IC (PLL 2) to divide by 10/20. That will give a much narrower bandwidth than the DDS chips are capable of (0.4-0.2MHz bandwidth). The memory for the DAC can be onboard with some DAC's or can be sent via SPI (and kept on the processor chip). Having just come out of a filtered PLL (ie. PLL 2), the synthesized frequency should be in phase and pretty well noise free. A line-driver into that to pump up the juice and bam.

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[*] posted on 18-10-2010 at 20:24


Years ago I had access to 3d FEA (Ansys ? I think it was). Had the nice feature of starting from a coarse grid, then progressively refining the grid only in those areas that needed it. Took some serious cpu horsepower though - would take all day to run one analysis. Interesting it was a Halbach array I was analysing (to find leakage induced eddycurrent losses in the motor housing). Don't have the software anymore, sorry.

As for using parts from one mfgr - thats no guarantee that things will work, or that you'll end up with the best solution. Every manufacturer has their strengths and weaknesses in their product portfolio.




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[*] posted on 19-10-2010 at 08:12


Quote: Originally posted by arsphenamine  

Y'know, you probably won't listen to this either, but seperating the circuitry into functional modules would allow for facile revisions as obligated by hardware (un)availability.

Oscillator, transmitter, demux, converter, CPU -- each gets their own PCB.

Like, duh, how much exposition does the value of modular design require?


Yuck, that's a retarded idea. Just shove signal quality out the door, why don't you?

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[*] posted on 19-10-2010 at 08:56


Quote: Originally posted by aliced25  
...

With the DDS chips being unfiltered and having multiple harmonic images, there is little reason to choose them over a multiple PLL design using a close-tolerance crystal running a DAC, multiply the original sine-wave to about 10-20 times the necessary wavelength (PLL 1), run it through a close-ish tolerance SAW filter (+/- 2MHz) and back through the IC (PLL 2) to divide by 10/20. That will give a much narrower bandwidth than the DDS chips are capable of (0.4-0.2MHz bandwidth). The memory for the DAC can be onboard with some DAC's or can be sent via SPI (and kept on the processor chip). Having just come out of a filtered PLL (ie. PLL 2), the synthesized frequency should be in phase and pretty well noise free. A line-driver into that to pump up the juice and bam.



Uh, you need to study how DDS circuits work a bit more, you seem to have some misconceptions on their capabilities; plus really try to design that concept of yours.


Anything in this image look familiar?




DDS.png - 6kB
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[*] posted on 19-10-2010 at 23:48


@ not_important

Have a look at that paper where the OUTPUT of the DDS chip was run back in through a second PLL to get everything back in phase. Now with those PLL's being dual fractional/integer-N type (each), then the DAC could be used with a quality crystal to generate a sine wave at a decent rate, say 10MHz, well within the range of mid-rate DAC's (which use RAM/ROM as the sine table - which is merely a recorded set of integers from full high to full low and back). As Analog Devices are using their own DDS chips for UHF frequencies by running them through a multiplier/integer-N PLL (and if that works, a second fractional-N PLL would also work), multiply the frequency by say 43, ie. 10MHz * 43 = 430MHz, through a 4MHz wide SAW Filter, then back through a fractional-n PLL to divide the signal by 10 (while the phase filter takes out/adjusts the crud), that should "hypothetically" give a 0.4MHz wide sine wave @ 43MHz (with everything in phase).

The SAW filter on the output of the first stage of the PLL should get rid of the kinks from the DAC every bit as well as a low-pass filter, while the Ref. Clock is the decent quartz crystal (actually 12MHz is needed for USB, so it is already on the board - something to consider). The Phase Accumulator/Sine Table are one and the same and are taken care of via scripting the DAC (actually some use just 1/4 of the table and reverse/invert the numbers to suit).

@ Twospoons

I'm trying my best to get hold of a 3D modeling program, every torrent I've used so far is fucked, while Radia works after a fashion, but it needs some funky ass scripting & Mathematica (the torrent for it works, or so I've been told) & I'm clueless on how to get it working at present.

@12AX7,

Using separate boards for ALL of the components seems excessive, especially when the data has to be sent from one to another inside a box that is going to be awfully close to a very strong magnet and a shitload of noise. I'm reading up on various grounding schemes at present, the noisiest part of the whole affair (on the analog side especially, exactly where it is NOT needed) is going to be powering the components, as each board would still need an LDO Regulator, I cannot see the sense in multiplying the noise. If anyone has a scheme whereby THAT can be filtered out on a separate board and supplied as and where needed with minimal fuss, that I'd like to see (notice they don't separate boards on phones? Analog, Digital, Frequency Synthesis, power supply, battery charging, etc. all on one board)...

PS Can anyone tell me why in god's name people are using 0.25mm traces (0.034mm) instead of 0.25mm Dia Wire? In terms of resistance the wire is about 1/10 of the trace, then again, the pipe is wider isn't it? Anyway, this is good for ideas.
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[*] posted on 20-10-2010 at 06:24


Quote: Originally posted by aliced25  
as each board would still need an LDO Regulator
Low dropout is more-or-less irrelevant to this application, because low-dropout doesn't mean the same as low-noise. Some LDO devices have low-noise characteristics, but not all do. LDO is principally an energy-efficiency technique, and it's principally useful for battery-operated devices. The other thing to remember is that low-noise for a consumer device, such as a cell phone, may not be considered low-noise in an instrumentation context.

The relevant concepts here are twin. For the power supply, you want high load rejection, which is the sensitivity of the output to changing load. On the powered-device side, you want a high power supply rejection (PSR), which is the sensitivity of the device behavior to changes in power supply. Note: the power supply itself has a PSR, often called line rejection, for example, the ability to reject spikes in the mains. A key point about consumer-grade chips is that they rarely need to worry about load rejection, particularly for digital loads.

This article has some example circuits and commentary about how to cut down regulator noise: http://www.wenzel.com/documents/finesse.html. Note the use of a pass resistor to cut down noise; this is absolutely not a lower-power technique.

Pretty much every accurate power supply circuit I've examined in any depth has two common features: a voltage reference and an error amplifier. To a first approximation, you can get a sense of the quality of a power supply by looking at the number and quality of the error amplifiers. For most applications a single error amplifier suffices. For some, though, you want cascaded ones.

I feel the need to stress that instrumentation electronics is significantly more than basic electronics, more of everything, particularly analysis. There's a whole chapter about it in The Art of Electronics, a book I recommend wholeheartedly. The authors, both at Harvard, have long experience designing instrumentation circuitry for physics and astronomy research.
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[*] posted on 20-10-2010 at 09:51


A discussion of several low noise DIY regulators is here

Collected circuit schematics are here

A recurrent theme is pre-regulation (LM317 or similar) followed by a low
noise wideband error amp. The op amp choice is important; the AD797
was ultimately rejected as too sensitive for high EMI environments and
was replaced by the AD817 or AD825.

Walt Jung, a primary reference for linear power supply regulation,
has collected some of his DIY regulator articles here
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[*] posted on 20-10-2010 at 10:23


Quote: Originally posted by 12AX7  

Yuck, that's a retarded idea. Just shove signal quality out the door, why don't you?
It's easier to make a few small widgets and then a large widget, than to make a large widget.

Modular design means each module can be tested and troubleshot separately. (Testing? WTF is that?)
If you have finite resources and want to complete a prototype more quickly,
it is good sense to make it work first and optimize it second.

The history of premature optimization is heavily littered with mistakes.

My favorite one is where testing couldn't
save an application from optimization.
Someone profiled live code to find hot spots,
found something executing 10k/sec.
The code block got hand-optimized.
Now executing at 50k/sec, it still had no effect on the system performance.
Wiser heads noted that the code under examination was the system idle loop.

ps, my chromosome 21 is just fine.
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[*] posted on 20-10-2010 at 10:49


Quote: Originally posted by aliced25  

Have a look at that paper where the OUTPUT of the DDS chip was run back in through a second PLL to get everything back in phase.


No. A PLL contains a controlled oscillator, limited by a LP filter in the rate of change in frequency and phase. The PLL locks to the signal applied, in the case you refer to that's the output of the DSS. The PLL is reducing jitter/short term instabilities, the same is done for xtal oscillators - a following PLL gives short term stability controlled by its LP filter while the crystal supplies long term stability.


Quote:
Now with those PLL's being dual fractional/integer-N type (each), then the DAC could be used with a quality crystal to generate a sine wave at a decent rate, say 10MHz, well within the range of mid-rate DAC's (which use RAM/ROM as the sine table - which is merely a recorded set of integers from full high to full low and back).


Note that a DDS generally contains a sine wave lookup table, or similar source of sine data, and a DAC converter - the same as you want to cobble together out of separate parts. I suspect the DDS will do better as there's no inter-package delay to deal with.

Much of the rest of the DDS is logic to generate the desired frequency - the clocking rate of the DAC in effect. If I understand what you're trying to do, you want to clock the DAC at a constant rate and change the lookup table contents. With a 10 MHZ clock you can only change your waveform cycle in steps of 100 nsec; 2 samples per cycle for 5 MHZ, 3 for 3.33333... MHz, 100 for 100 KHZ, 99 for 101,0101... KHz, 101 for 99,0099099... KHz. Without tweaking the clock you can't hit exactly 99 KHz.


Quote:
As Analog Devices are using their own DDS chips for UHF frequencies by running them through a multiplier/integer-N PLL (and if that works, a second fractional-N PLL would also work), multiply the frequency by say 43, ie. 10MHz * 43 = 430MHz, through a 4MHz wide SAW Filter, then back through a fractional-n PLL to divide the signal by 10 (while the phase filter takes out/adjusts the crud), that should "hypothetically" give a 0.4MHz wide sine wave @ 43MHz (with everything in phase).


A pure sine wave has a width of zero, a "0.4MHz wide sine wave @ 43MHz" is jumping around over 1% of its frequency - rather noisy. Are you trying to say 'tunable over 0,4 MHz' ? If so, then consider using better terminology.

Quote:
The SAW filter on the output of the first stage of the PLL should get rid of the kinks from the DAC every bit as well as a low-pass filter, while the Ref. Clock is the decent quartz crystal (actually 12MHz is needed for USB, so it is already on the board - something to consider). The Phase Accumulator/Sine Table are one and the same and are taken care of via scripting the DAC (actually some use just 1/4 of the table and reverse/invert the numbers to suit).


1) A SAW at that point is overkill, more expensive than simple LP filters and possibly requiring buffer amps for matching.

2) The crystal needs for a USB interface is much less demanding than the reference for a NMR. Remember everyone else has been talking OCXT to meet the demands.

3) How are you proposing to "reverse/invert" the table data? If not done in hardware then the delays at transition points will cause jitter and uncertainty in the frequency.


Quote:
PS Can anyone tell me why in god's name people are using 0.25mm traces (0.034mm) instead of 0.25mm Dia Wire? In terms of resistance the wire is about 1/10 of the trace, then again, the pipe is wider isn't it? Anyway, this is good for ideas.


Because traces are repeatable and automatble, wires aren't. For commercial products those are very important, for research work at that size of connections PCBs can be more convenient as design software can generate the trace layout.


As for voltage regulators - that's been pretty well covered.
Quote:
(notice they don't separate boards on phones? Analog, Digital, Frequency Synthesis, power supply, battery charging, etc. all on one board)...

However mobile phones are intended to slip into a pocket; I doubt you're planning to do so with a NMR, the magnet size along is well beyond that.* Also the designers expend effort and time to make those designs work well, I doubt you have the tools - software and hardware - used to do that job.


* this excludes some of the micro-NMR designs being kicked about. Fabbing those might be a bit of a challenge.



[Edited on 20-10-2010 by not_important]
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[*] posted on 20-10-2010 at 14:33


Quote: Originally posted by aliced25  
You can cancel the hump out by turning the 4 circular magnets, however it will only go so far.

How does one know when the hump is canceled,i.e.,homogeneity improves?

Perhaps a test method needs discussion.

How does one safely rotate and stabilize magnets that exert over 100 lbs attractive force?

These questions give me cause for concern.
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[*] posted on 20-10-2010 at 15:48


@ arsphenamine

The Magnets are aligned with great care, the main difficulty lies in determining the resultant field, Teslameters/Magnometers/Reed Switches, etc. are all built with a 1% accuracy, that is way too low for this application - however several groups have tested and adjusted their field by performing <sup>1</sup>H-NMR experiments on water/soluble copper and compared their results to what is expected. As to rotation, there is going to need to be some way of holding the magnet sufficiently tightly so that it remains in the orientation in which it is aligned, and does not self-align - another part of the problem.

@ not_important

This tutorial, MT-031 Grounding Data Converters and Solving the Mystery of "AGND" and "DGND" pretty much explains what we are trying to do, there is a DSP in the center of the two planes, with both DAC's & ADC's plus power supply to deal with. There are numerous Tech. Bulletins on the subject, including the use of an isolator to physically separate the Analog & Digital parts of the board. There are even online books & chapters on the subject.

As to the use of the DAC, running a 100MSPS DAC to output a 10MHz signal (AD App. Note) is not exactly unusual (AD Tutorial, neither is the use of what is essentially playback - a set of values is "played" via the DAC to give the signal output (Basics of DDS). However the images & harmonics that come with that make the digitally approximated sine wave less than narrow-bandwidth (thus my problem with the DDS chips - there are circuit notes where they discuss using these for synthesizing much higher bands than are possible with the first-order). They utilize multiple-component 7-8th Order Filters as Low-Pass filters, whereas the SAW filters have smaller bandwidth passbands, are cheaper and use less components. Running the generated signal through a PLL to increase it to the UHF Band is also well and truly discussed by the AD Team, running that wide bandwidth signal through a SAW Filter to remove the images, spurs, etc. seems logical, running the narrow-bandwidth UHF Signal through a fractional-N PLL to get the smaller band signal also seems intuitive.

As the various DDS Chips (with the associated phase & spur/harmonic noise) have been used in micro-NMR before, a lower cost, narrower bandwidth solution using minimal parts appeals. The use of the DAC generated signal as the input for the PLL is not new, nor is the fractional/integer-n modification of it. The SAW filter is less demanding than that multipart analog filter design & a decent crystal should suffice, given the width of the bandwidth used by others using a DDS chip without serious filtration.

So the only reason why traces are used is the difficulty in reproducing the same wire width? Seems awfully odd, especially given that wire is used in chip manufacture (with ultrasonic welding). I'm just trying to comprehend why it is better to purchase copper foil, a photopolymer, make a negative, expose it, remove the unexposed layer, etch the copper back off the board, then remove the rest of the polymer, tin the copper and then lacquer the board... It hardly seems efficient does it?

[Edited on 20-10-2010 by aliced25]
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[*] posted on 20-10-2010 at 18:30


So what is all this DAC BS about?

Has someone forgotten that a squarewave is 90% fundamental?? You put a filter on it. 4th order bandpass will do at least -30dB attenuation of harmonics, more if you add a trap for the 3rd harmonic, and still more if you add a resonator to accentuate the fundamental. What do the harmonics matter, anyway? There aren't harmonic protons. So what if it's wasted power, the harmonics ares down >= 10dB so they hardly affect efficiency.

RF excitation does not need to be very accurate. The spectrum of a 10us RF burst is necessarily spread out by the very act of windowing it. The spectrum looks like a sinc function, with -6dB points at f_o +/- 60kHz, regardless of whether the signal came from NIST or a redneck's car radio!

The ONLY thing that a reference is required for is conversion. The long thing. The FID capture that takes ten seconds. The signal that's actually long enough to observe narrow peaks.

Power supplies are even less of a concern than in cell phones (which is a big concern, BTW, because they pick signals out of the noise floor). With only two or three discrete frequencies of interest, it is ridiculously easy to filter.

This isn't audio, where you're filtering a three decade band, or an oscilloscope, where you're watching DC to light. The preamp, converter and FFT are all completely insensitive to interference outside of the passband. There could be gobs of trash at say, 41MHz, which ends up as a 1MHz image after the converter, which is about 23 times above the sample rate and trivial to filter.

Aliced25: Beats me, but considering that 99.97% of all electronics manufactured today are made of printed circuit boards, I think you'll discover the answer easily enough.

Tim




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[*] posted on 21-10-2010 at 08:35


Quote: Originally posted by aliced25  
The Magnets are aligned with great care...
How? By big chunky guys wielding velvet-covered pipe wrenches?
Quote:
the main difficulty lies in determining the resultant field, Teslameters/Magnometers/Reed Switches,etc. are all built with a 1% accuracy, that is way too low for this application
Accuracy != Precision != Resolution.

My bathroom scale is 5 lbs off, but I'm impressed that it detects
a difference when I add or remove a beer by the usual methods.

For field homogeneity measurements, repeatable resolution is more important than absolute accuracy.

IF you have a Hall sensor (not an IC), you can detect sub-Gauss field differences.

Quote:
- however several groups have tested and adjusted their field by performing 1H-NMR experiments on water/soluble copper and compared their results to what is expected.
What are the expected results? How did they adjust it?

Those indeterminate groups are most likely filling the field bore with a water bottle, in which case, the field is averaged over most of the bore volume.

You infer field inhomogeneity from peak height, broadening and slope asymmetry (and there are patented statistical analytic methods to do this), but the method is spatially too lo-rez to determine the inhomogeneity location.

Spinning an ISO 5mm sample tube in the field sweet spot is more germane but the same arguments apply.

If you can't find it, you can't correct it.

Since this design uses magnets of unknown homogeneity, a direct test method is essential.
You gotta poke a tiny sensor in the magnet bore.

So you may wonder, "Um. Now how do I position a Hall sensor, and with what resolution?"

An XY table or jig will do.

Your required resolution is the sensor die size, about 0.3mm square, about ~ .012 inch in each axis.

It's hard to find a commercial XY table that crappy but it's easy to build one.

Instructables has many variations on the XY position methods. By the Principle of Maximum Laziness, I favor the ones that use page scanners -- gut the electronics and put in two cheap stepper controllers.

Quote:
As to rotation, there is going to need to be some way of holding the magnet sufficiently tightly...
Talk to a machinist. Get a shop tour if you can, because machinists have some of the coolest toys in the world.
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[*] posted on 21-10-2010 at 15:28


Well, according to Analog Device's "A Technical Tutorial on Digital Signal Synthesis"
Quote:
In its simplest form, a direct digital synthesizer can be implemented from a precision reference clock, an address counter, a programmable read only memory (PROM), and a D/A converter.

In this case, the digital amplitude information that corresponds to a complete cycle of a sinewave is stored in the PROM. The PROM is therefore functioning as a sine lookup table. The address counter steps through and accesses each of the PROM’s memory locations and the contents (the equivalent sine amplitude words) are presented to a high-speed D/A converter. The D/A converter generates an analog sinewave in response to the digital input words from the PROM. The output frequency of this DDS implementation is dependent on 1.) the frequency of the reference clock, and 2.) the sinewave step size that is programmed into the PROM. While the analog output fidelity, jitter, and AC performance of this simplistic architecture can be quite good, it lacks tuning flexibility.
...
With the introduction of a phase accumulator function into the digital signal chain, this architecture becomes a numerically-controlled oscillator which is the core of a highly-flexible DDS device.


So what you've been proposing to build from parts is a simple DDS, save that you are not using a PROM to hold the waveform. It will have similar problems to a conventional DDS chip unless you use a wide and deep memory. The outboarded PPLs used to generate the clock(s) and clean up the output would do the same for an integrated DDS chip.


You might find it useful to do a perusal of this http://www.xs4all.nl/~martein/pa3ake/hmode/index.html


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[*] posted on 21-10-2010 at 21:50


Quote: Originally posted by aliced25  

So the only reason why traces are used is the difficulty in reproducing the same wire width? Seems awfully odd, especially given that wire is used in chip manufacture (with ultrasonic welding). I'm just trying to comprehend why it is better to purchase copper foil, a photopolymer, make a negative, expose it, remove the unexposed layer, etch the copper back off the board, then remove the rest of the polymer, tin the copper and then lacquer the board... It hardly seems efficient does it?

[Edited on 20-10-2010 by aliced25]


Two words: mass production.

There was a time when wirewrap was the way to build electronics, and to be fair it has a couple of advantages: lower crosstalk, reliability. But it is slow to build, and bulky, and silver plated wire and connectors aren't exactly cheap.

PCBs give you repeatability, a mounting surface, fast assembly, variable trace widths, controlled impedance, delay matching, heatsinking ....
And its cheap because everyone does it.




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